1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to systems and methods for testing semiconductor memory devices.
2. Description of Related Art
Integrated circuit memory devices are widely used in consumer and commercial electronics. As the integration density of these devices continues to increase, the number of cells in a memory cell array may continue to increase. With the increased number of memory cells, it may become increasingly difficult to test the memory cell array.
As is well known to those of skill in the art, a memory cell array generally includes a plurality of data line outputs. In a normal, non-test mode, the data on the data line outputs can be transmitted to global output lines. In contrast, in a parallel bit test mode, a plurality of data bits can be concurrently output for comparison testing in a separate parallel bit test circuit.
A conventional semiconductor memory device tester may use a parallel bit test (PBT) technique to test more than one semiconductor memory device at the same time. The PBT technique does not receive or output data through all of the data I/O pads of the semiconductor memory devices, but only through a predetermined number of data I/O pads, thereby allowing for simultaneous testing of a larger number of semiconductor memory devices.
For example, if a tester has 32 data I/O terminals and a semiconductor memory device operating at a single data rate (SDR) receives or outputs 16-bit data, only two semiconductor memory devices can be tested simultaneously. However, using the PBT technique, 4 or 8 semiconductor memory devices can be tested at the same time, as data can be received or output through 8 or 4 data I/O pads, respectively.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device having a double data rate. The semiconductor memory device of FIG. 1 includes a memory cell array 10, a column redundant memory cell array 12, a row redundant memory cell array 14, a comparator 16, and a write data multiplexer 18.
In FIG. 1, DQ1 to DQ16 represent data I/O pads. The semiconductor memory device of FIG. 1 receives or outputs 16-bit data at a double data rate through the data I/O pads DQ1 to DQ16. The memory cell array 10 includes even memory cell array 10-1 and odd memory cell array 10-2. The even memory cell array 10-1 includes 4 memory cell regions {circle around (1)} to {circle around (4)}, and the odd memory cell array 10-2 includes 4 memory cell regions {circle around (5)} to {circle around (8)}. ECSL1 represents a column selecting signal line for selecting 4 bit lines of each of the memory cell regions {circle around (1)} and {circle around (3)} of the even memory cell array 10-1, and ECSL2 represents a column selecting signal line for selecting 4 bit lines of each of the memory cell regions {circle around (2)} and {circle around (4)} of the even memory cell array 10-1. OCSL1 represents a column selecting signal line for selecting 4 bit lines of each of the memory cell regions {circle around (5)} and {circle around (7)} of the odd memory cell array 10-2, and OCSL2 represents a column selecting signal line for selecting 4 bit lines of each of the memory cell regions {circle around (6)} and {circle around (8)} of the odd memory cell array 10-2. WL1 represents a row selecting signal line for selecting word lines of each of the memory cell regions {circle around (1)}, {circle around (2)}, {circle around (5)}, and {circle around (6)} of the memory cell array 10, and WL2 represents a row selecting signal line for selecting word lines of each of the memory cell regions {circle around (3)}, {circle around (4)}, {circle around (7)}, and {circle around (8)} of the memory cell array 10. RCSL represents a redundant column selecting signal line of the column redundant memory cell array 12, and RWL represents a redundant row selecting signal line of the row redundant memory cell array 14. Finally, BL represents a bit line of the memory cell array 10.
Referring to FIG. 1, the memory cell array 10 includes the even memory cell array 10-1 and the odd memory cell array 10-2. The even memory cell array 10-1 includes 4 memory cell regions {circle around (1)} to {circle around (4)} for storing data in locations selected by the row selecting signal lines WL1 and WL2 and the column selecting signal lines ECSL1 and ECSL2. The 4 memory cell regions {circle around (1)} to {circle around (4)} each respectively receive 4-bit data EDI1˜4, EDI5˜8, EDI9˜12, and EDI13˜16 in a write operation mode, and each respectively output 4-bit data EDO1˜4, EDO5˜8, EDO9˜12, and EDO13˜16 in a read operation mode. The odd memory cell array 10-2 includes 4 memory cell regions {circle around (5)} to {circle around (8)} for storing data in locations selected by the row selecting signal lines WL1 and WL2 and the column selecting signal lines OCSL1 and OCSL2. The 4 memory cell regions {circle around (5)} to {circle around (8)} each respectively receive 4-bit data ODI1˜4, ODI5˜8, ODI9˜12, and ODI13˜16 in a write operation mode, and each respectively output 4-bit data ODO1˜4, ODO5˜8, ODO9˜12, and ODO13˜16 in a read operation mode. The column redundant memory cell array 12 is used to replace a column selecting signal line with a redundant column selecting signal line when a defect occurs in the memory cells connected to the column selecting signal lines ECSL1, ECSL2, OCSL1, and OCSL2 of the memory cell array 10. The row redundant memory cell array 14 is used to replace a row select line with a redundant row select line when a defect occurs in the memory cells connected to the row select lines WL1 and WL2 of the memory cell array 10. The comparator 16 compares, by 4 bits, test data EDO1˜4, EDO5˜8, EDO9˜12, EDO13˜16, ODO1˜4, ODO5˜8, ODO9˜12, and ODO13˜16 output from the memory cell regions {circle around (1)} to {circle around (8)}, respectively, to generate 8-bit comparison result data MA1 to MA8 in a parallel bit test operation mode. The 8-bit comparison result data MA1 to MA8 is output from the memory device through the data I/O pads DQ1, DQ3, DQ5, DQ7, DQ9, DQ11, DQ13, and DQ15. That is, the comparison result data obtained from comparing the 4-bit data output from the memory cell regions {circle around (1)} to {circle around (8)} are output from the memory device through 8 data I/O pads DQ1, DQ3, DQ5, DQ7, DQ9, DQ11, DQ13, and DQ15. The write data multiplexer 18, in a parallel bit test mode, extends 4-bit (or 8-bit) data received from the data I/O pads DQ1, DQ5, DQ9, and DQ13 (or DQ1, DQ3, DQ5, DQ7, DQ9, DQ11, DQ13, and DQ15) to 32-bit data and then outputs 4-bit data EDI1˜4, EDI5˜8, EDI9˜12, EDI13˜16, ODI1˜4, ODI5˜8, ODI9˜12, and ODI13˜16 to the memory cell regions {circle around (1)} to {circle around (8)}, respectively. At this time, 4-bit test data are equally stored in the respective memory cell regions {circle around (1)} to {circle around (8)}.
FIG. 2 is a block diagram illustrating the comparator 16 of the semiconductor memory device of FIG. 1 in greater detail. The comparator of FIG. 2 includes a first comparator including blocks 30-1 to 30-16 and a second comparator including blocks 32-1 to 32-8. Operation of the comparator is explained below.
Referring to FIG. 2, the comparator blocks 30-1 to 30-8 compare 2-bit data pairs EDO1, 2 to EDO15, 16, which are output from the even memory cell array 10-1, to generate comparison result data. If both bits of the pair match, comparison result data having a “high” level is generated, whereas if both bits of the pair do not match, comparison result data having a “low” level is generated. Similarly, comparator blocks 30-9 to 30-16 compare-bit data pairs ODO1, 2 to ODO15, 16, which are output from the odd memory cell array 10-2, to generate comparison result data. If both bits of the pair match, comparison result data having a “high” level is generated, whereas if both bits of the pair do not match, comparison result data having a “low” level is generated. Comparator blocks 32-1 to 32-4 compare the 2-bit comparison result data output from the comparators 30-1 to 30-8 in order to output comparison result data MA1 to MA4 from the memory device through data I/O pads DQ1, DQ3, DQ5, and DQ7, respectively. The comparators 32-5 to 32-8 compare 2-bit comparison result data output from the comparators 30-9 to 30-16 to output the comparison result data MA5 to MA8 from the memory device through data I/O pads DQ9, DQ11, DQ13, and DQ15, respectively.
That is, the comparator 16 of FIG. 2 compares 4-bit data output from the memory cell regions {circle around (1)} to {circle around (8)} and outputs the comparison result data MA1 to MA8 from the memory device to the tester using data I/O pads DQ1, DQ3, DQ5, DQ7, DQ9, DQ11, DQ13, and DQ15.
The semiconductor memory device tester determines the addresses of defective memory cells in memory cell regions {circle around (1)} to {circle around (8)} based on the comparison result data MA1 to MA8 output from the data I/O pads DQ1, DQ3, DQ5, DQ7, DQ9, DQ11, DQ13, and DQ15. For example, when the comparison result data MA1 output from the data I/O pad DQ1 has a “low” level, locations within memory cell region {circle around (1)} are regarded as being defective.
However, when the 8-bit data (MA1 to MA8) that is output from the comparators 32-1 to 32-8 is further compared by 2 bits in order to reduce the number of data I/O pads used for a read operation, the tester may not be able to correctly determine the addresses of defective memory cell locations in regions {circle around (1)} to {circle around (8)}. Thus, a conventional semiconductor memory device which can receive or output 16-bit data may require at least 8 data I/O pads for the PBT. As a result, the number of the semiconductor memory devices which can be tested simultaneously is limited.